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Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
DESCRIPTION
The NE/SE564 is a versatile, high guaranteed frequency phase-locked loop designed for operation up to 50MHz. As shown in the Block Diagram, the NE/SE564 consists of a VCO, limiter, phase comparator, and post detection processor.
PIN CONFIGURATIONS
D, N Packages
V+ LOOP GAIN CONTROL INPUT TO PHASE COMP FROM VCO LOOP FILTER LOOP FILTER FM/RF INPUT BIAS FILTER GND 1 2 3 4 5 6 7 8 16 TTL OUTPUT 15 HYSTERESIS SET 14 ANALOG OUT 13 FREQ. SET CAP 12 FREQ. SET CAP 11 VCO OUT 2
FEATURES
* Operation with single 5V supply * TTL-compatible inputs and outputs * Guaranteed operation to 50MHz * External loop gain control * Reduced carrier feedthrough * No elaborate filtering needed in FSK applications * Can be used as a modulator * Variable loop gain (externally controlled)
APPLICATIONS
10 V+ 9 VCO OUT TTL
TOP VIEW
SR01025
* High speed modems * FSK receivers and transmitters * Frequency Synthesizers
ORDERING INFORMATION
DESCRIPTION 16-Pin Plastic Small Outline (SO) Package 16-Pin Plastic Dual In-Line Package (DIP) 16-Pin Plastic Dual In-Line Package (DIP)
Figure 1. Pin Configuration
* Signal generators * Various satcom/TV systems * pin configuration
TEMPERATURE RANGE 0 to +70C 0 to +70C -55 to +125C ORDER CODE NE564D NE564N SE564N DWG # SOT109-1 SOT38-4 SOT38-4
BLOCK DIAGRAM
V+ 4 5 1 14
LIMITER 6
PHASE COMPARATOR
2 DC
7
3 11 9 VCO 10 12 13 8 AMPLIFIER
RETRIEVER SCHMITT TRIGGER
16
POST DETECTION PROCESSOR
15
SR01026
Figure 2. Block Diagram
1994 Aug 31
1
853-0908 13720
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
ABSOLUTE MAXIMUM RATINGS
SYMBOL V+ Supply voltage Pin 1 Pin 10 Sink Max (Pin 9) and sourcing (Pin 11) Bias current adjust pin (sinking) Power dissipation Operating ambient temperature NE SE TSTG Storage temperature range NOTE: Operation above 5V will require heatsinking of the case. PARAMETER RATING 14 6 11 1 600 0 to +70 -55 to +125 -65 to +150 UNITS V V mA mA mW
IOUT IBIAS PD TA
C C C
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = 5V; TA = 0 to 25C; fO = 5MHz, I2 = 400A; unless otherwise specified. LIMITS SYMBOL PARAMETER Maximum VCO frequency TEST CONDITIONS MIN C1 = 0 (stray) Input > 200mVRMS TA = 25C TA = 125C TA = -55C TA = 0oC TA = 70C Input > 200mVRMS, R2 = 27 fO = 5MHz, TA = -55C to +125C TA = 0 to +70C = 0 to +70C fO = 5MHz, TA = -55C to +125C TA = 0 to +70C C1 = 91pF RC = 100 "Internal" VCC = 4.5V to 5.5V Modulation frequency: 1kHz fO = 5MHz, input deviation: 2%T = 25C 1%T = 25C 1%T = 0C 1%T = -55C 1%T = 70C 1%T = 125C Deviation: 1% to 8% Std. condition, 1% to 10% dev. Std. condition, 30% AM Modulation frequency: 1kHz fO = 5MHz, input deviation: 1% VCC = 4.5V VCC = 5.5V VCC = 5V I1, I10 VOUT = 5V, Pins 16, 9 IOUT = 2mA, Pins 16, 9 IOUT = 6mA, Pins 16, 9 4 50 40 20 50 SE564 TYP 65 70 30 80 MAX MIN 45 40 LIMITS NE564 TYP 60 70 % of fO 70 40 20 30 500 300 1500 600 800 500 5 3 6 8 3.5 5 3 6.5 8 MHz % of fO PPM/oC 20 30 % of fO MAX MHz UNITS
Lock range
Capture range
VCO frequency drift with temperature
VCO free-running frequency VCO frequency change with supply voltage
Demodulated output voltage
16 8 6 12
28 14 10 16 1 40 35 16 8
28 14 13 15 1 40 35
mVRMS mVRMS mVRMS mVRMS mVRMS mVRMS % dB dB mVRMS mVRMS 60 20 0.6 0.8 mA A V V
Distortion S/N Signal-to-noise ratio AM rejection Demodulated output at operating voltage ICC Supply current Output "1" output leakage current "0" output voltage
7 8
12 14 45 1 0.3 0.4 60 20 0.6 0.8
7 8
12 14 45 1 0.3 0.4
1994 Aug 31
2
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS
Lock Range vs Signal Input
1000 8 6 4 INPUT SIGNAL LEVEL - mV IPIN = 0A IPIN = 400A
2
VCO Capacitor vs Frequency
106
2
105 CAPACITANCE pF 104 103 102 10 1
2
100 8 6 4
2
VCC 5V fo = 5MHz
.1
1
10
102
103
104
105
FREQUENCY kHz
10 0.7 0.8 0.9 1.0 1.1 1.2 1.3 NORMALIZED LOCK RANGE
Typical Noirmalized VCO Frequency as a Function of Pin 2 Bias Current
NORMALIZED VCO FREQUENCY
Typical Noirmalized VCO Frequency as a Function of Pin 2 Bias Current
NORMALIZED VCO FREQUENCY
Typical Noirmalized VCO Frequency as a Function of Temperature
NORMALIZED VCO FREQUENCY
1.10 VCO FREQUENCY: 50MHz 1.05
1.01 1.00 0.99 0.98 0.97 0.96 -600A
FREQUENCY: 50MHz
1.10 1.05 1.00 0.95 0.90
BIAS CURRENT: -- 200A FREQUENCY: 5MHz
1.00
0.95
0.90
FREQUENCY: 500MHz BIAS CURRENT: -- 200A
-400
-200
0
+200
-600A -400
-200
0
+200
+400
-50
-25
25
0
25
50
75
100
125
BIAS CURENT (A), PIN 2
BIAS CURENT (A), PIN 2
TEMPERATURE
(INoC)
SR01027
Figure 3. Typical Performance Characteristics
1994 Aug 31
3
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
VD - PHASE COMPARATOR'S OUTPUT VOLTAGE IN mV
800 VCO FREQUENCY IN MHz 1.6 IBIAS = 800A IBIAS = 00A fo = 1.0MHz 200 1.4
IBIAS = 200A 600 IBIAS = 400A IBIAS = 800A 400 IBIAS = 0A
1.2
0 40 60 100 120 140 160 0 - PHASE ERROR IN DEGREES -400 -200 200 400 600 800 VDIN mV
-200
.8
-400
.6
-600
-800
Variation of the Comparator's Output Voltage vs Phase Error and Bias Current (KD)
VCO Output Frequency as a Function of Input Voltage and Bias Current (KO)
SR01028
Figure 4. Typical Performance Characteristics (cont.)
TEST CIRCUIT
+5V
R3 R1
1K
INPUT
C3 6 0.1F 1K 7 C2 430pF C2 430pF R2 5 R2 4
1
2
10
16
9 3
15 pF
390
VCO OUYPUT
DEMODULATED OUTPUT 0.1F
14 564 13 C1 12 8
SR01029
Figure 5. Test Circuit
1994 Aug 31
4
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
FUNCTIONAL DESCRIPTION (Figure 6)
The NE564 is a monolithic phase-locked loop with a post detection processor. The use of Schottky clamped transistors and optimized device geometries extends the frequency of operation to greater than 50MHz. In addition to the classical PLL applications, the NE564 can be used as a modulator with a controllable frequency deviation. The output of the PLL can be written as shown in the following equation: VO = (fIN - fO) KVCO (1)
Phase Comparator Section
The phase detection processor consists of a doubled-balanced modulator with a limiter amplifier to improve AM rejection. Schottky-clamped vertical PNPs are used to obtain TTL level inputs. The loop gain can be varied by changing the current in Q4 and Q15 which effectively changes the gain of the differential amplifiers. This can be accomplished by introducing a current at Pin 2.
Post Detection Processor Section
The post detection processor consists of a unity gain transconductance amplifier and comparator. The amplifier can be used as a DC retriever for demodulation of FSK signals, and as a post detection filter for linear FM demodulation. The comparator has adjustable hysteresis so that phase jitter in the output signal can be eliminated. As shown in the equivalent schematic, the DC retriever is formed by the transconductance amplifier Q42 - Q43 together with an external capacitor which is connected at the amplifier output (Pin 14). This forms an integrator whose output voltage is shown in the following equation: VO = gM C2 VINdt (3)
KVCO = conversion gain of the VCO fIN = frequency of the input signal fO = free-running frequency of the VCO The process of recovering FSK signals involves the conversion of the PLL output into logic compatible signals. For high data rates, a considerable amount of carrier will be present at the output of the PLL due to the wideband nature of the loop filter. To avoid the use of complicated filters, a comparator with hysteresis or Schmitt trigger is required. With the conversion gain of the VCO fixed, the output voltage as given by Equation 1 varies according to the frequency deviation of fIN from fO. Since this differs from system to system, it is necessary that the hysteresis of the Schmitt trigger be capable of being changed, so that it can be optimized for a particular system. This is accomplished in the 564 by varying the voltage at Pin 15 which results in a change of the hysteresis of the Schmitt trigger. For FSK signals, an important factor to be considered is the drift in the free-running frequency of the VCO itself. If this changes due to temperature, according to Equation 1 it will lead to a change in the DC levels of the PLL output, and consequently to errors in the digital output signal. This is especially true for narrowband signals where the deviation in fIN itself may be less than the change in fO due to temperature. This effect can be eliminated if the DC or average value of the signal is retrieved and used as the reference to the comparator. In this manner, variations in the DC levels of the PLL output do not affect the FSK output.
gM = transconductance of the amplifier C2 = capacitor at the output (Pin 14) VIN = signal voltage at amplifier input With proper selection of C2, the integrator time constant can be varied so that the output voltage is the DC or average value of the input signal for use in FSK, or as a post detection filter in linear demodulation. The comparator with hysteresis is made up of Q49 - Q50 with positive feedback being provided by Q47 - Q48. The hysteresis is varied by changing the current in Q52 with a resulting variation in the loop gain of the comparator. This method of hysteresis control, which is a DC control, provides symmetric variation around the nominal value.
Design Formula
The free-running frequency of the VCO is shown by the following equation: fO 1 22 RC (C1 + CS) (4)
VCO Section
Due to its inherent high-frequency performance, an emitter-coupled oscillator is used in the VCO. In the circuit, shown in the equivalent schematic, transistors Q21 and Q23 with current sources Q25 - Q26 form the basic oscillator. The approximate free-running frequency of the oscillator is shown in the following equation: 1 fO 22 RC (C1 + CS) RC = R19 = R20 = 100 (INTERNAL) C1 = external frequency setting capacitor CS = stray capacitance Variation of VD (phase detector output voltage) changes the frequency of the oscillator. As indicated by Equation 2, the frequency of the oscillator has a negative temperature coefficient due to the monolithic resistor. To compensate for this, a current IR with negative temperature coefficient is introduced to achieve a low frequency drift with temperature. (2)
RC = 100 C1 = external cap in farads CS = stray capacitance The loop filter diagram shown is explained by the following equation: fS = 1 (First Order) 1 + sRC3 (5)
R = R12 = R13 = 1.3k (Internal)* By adding capacitors to Pins 4 and 5, a pole is added to the loop transfer at = 1 RC3 NOTE: *Refer to Figure 6.
1994 Aug 31
5
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
EQUIVALENT SCHEMATIC
1 R4 LIMITER 900 10k 10k R5 R6 7 10k PHASE COMPARATOR R12 1.3k R13 1.3k 5 .75mA R14 10k Q12 DC RETRIEVER 14 Q16 3 2 D5 R34 6.2K D11 D10 R27 10k R26 10k Q22 Q45 R35 100 Q33 R21 10k Q25 Q26 Q28 R23 680 R22 2k D9 12 13 D8 AMPLIFIER Q27 R36 100 R18 4.3k R16 4.3k Q46 R48 10k Q58 D11 R33 6.2K Q40 Q41 1 SCHMITT TRIGGER R12 10K R10 500 R11 500 15
R1
R2
2k R3
D1
2k
D2 Q7 Q9 Q10
R8
Q11
6
Q2 Q3 Q1 Q5
QR R7 1k R8 1k D3 R10 6.8k R11 6.8k Q6 Q13 Q14
Q47
Q4 D4
Q15
Q48
8 6.2k R20 R19 62k 10 Q35 11 9 Q32 Q31 Q36 Q34 Q20 100 Q42 Q41
16
R17
Q49
Q50 R29 10k D12
Q17 Q14 Q23 Q24 Q15
Q42
Q44
Q30 R33 750 Q29 R34 750 Q21
Q22
Q37 D7 D6 Q39
Q31
VCO
SR01030
Figure 6. Equivalent Schematic
LOCK RANGE ADJUSTMENT I2 0.01F
LOOP FILTER 0.01F 0.47F FM INPUT fO = 5MHz fM = 1kHz BIAS FILTER .01F 3 1 8 10 9 12 13 80pF fO = 5MHz FREQUENCY SET CAP 1k 6 1k 7 564 15 14 0.1F ANALOG OUT 1kHz POST DETECTION FILTER 16 2 11 4 5
5V
5V
SR01031
Figure 7. FM Demodulator at 5V
1994 Aug 31
6
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
APPLICATIONS FM Demodulator
The NE564 can be used as an FM demodulator. The connections for operation at 5V and 12V are shown in Figures 7 and 8, respectively. The input signal is AC coupled with the output signal being extracted at Pin 14. Loop filtering is provided by the capacitors at Pins 4 and 5 with additional filtering being provided by the capacitor at Pin 14. Since the conversion gain of the VCO is not very high, to obtain sufficient demodulated output signal the frequency deviation in the input signal should be 1% or higher.
2k MODULATING INPUT 1kHz 0.47F 1kHz 1k 7 .01F 3 1 8 10 9 12 13 80pF 564 15 14 6 16 2 11 4 5 I2
5V FINE FREQUENCY ADJUSTMENT
Modulation Techniques
The NE564 phase-locked loop can be modulated at either the loop filter ports (Pins 4 and 5) or the input port (Pin 6) as shown in Figure 9. The approximate modulation frequency can be determined from the frequency conversion gain curve shown in Figure 10. This curve will be appropriate for signals injected into Pins 4 and 5 as shown in Figure 9.
fO = 5MHz FREQUENCY SET CAP 5V 1k MODULATED OUTPUT (TTL)
I2 LOCK RANGE ADJUSTMENT 0.01F
5V
SR01033
Figure 9. Modulator
LOOP FILTER 0.01F FM INPUT fO = 5MHz fM = 1kHz BIAS FILTER 0.47F 6 1k 7 .01F 3 1 8 10 9 12 13 80pF fO = 5MHz FREQUENCY SET CAP 200 1k 564 14 0.1F POST DETECTION FILTER 15 16 2 11 4 5 ANALOG OUT 1kHz
The lock range graph indicates that the +1.0MHz frequency deviations will be within the lock range for input signal levels greater than approximately 50mV with zero Pin 2 bias current. (While strictly this figure is appropriate only for 50MHz, it can be used as a guide for lock range estimates at other fO' frequencies). The hysteresis was adjusted experimentally via the 10k potentiometer and 2k bias arrangement to give the waveshape shown in Figure 12 for 20k, 500k, 2M baud rates with square wave FSK modulation. Note the magnitude and phase relationships of the phase comparators' output voltages with respect to each other and to the FSK output. The high-frequency sum components of the input and VCO frequency also are viable as noise on the phase comparator's outputs.
.01F
12V
SR01032
OUTLINE OF SETUP PROCEDURE
1. Determine operating frequency of the VCO: IF/ N in feedback loop, then fO = N x fIN. 2. Calculate value of the VCO frequency set capacitor: CO 1 2200 fO
Figure 8. FM Demodulator at 12V
FSK Demodulation
The 564 PLL is particularly attractive for FSK demodulation since it contains an internal voltage comparator and VCO which have TTL compatible inputs and outputs, and it can operate from a single 5V power supply. Demodulated DC voltages associated with the mark and space frequencies are recovered with a single external capacitor in a DC retriever without utilizing extensive filtering networks. An internal comparator, acting as a Schmitt trigger with an adjustable hysteresis, shapes the demodulated voltages into compatible TTL output levels. The high-frequency design of the 564 enables it to demodulate FSK at high data rates in excess of 1.0M baud. Figure 10 shows a high-frequency FSK decoder designed for input frequency deviations of +1.0MHz centered around a free-running frequency of 10.8MHz. the value of the timing capacitance required was estimated from Figure 8 to be approximately 40pF. A trimmer capacitor was added to fine tune fO' 10.8MHz.
3. Set I2 (current sinking into Pin 2) for 100A. After operation is obtained, this value may be adjusted for best dynamic behavior, V * 1.3V and replace with fixed resistor value of R2 = CC . IB
2
4. Check VCO output frequency with digital counter at Pin 9 of device (loop open, VCO to det.). Adjust CO trim or frequency adj. Pins 4 - 5 for exact center frequency, if needed. 5. Close loop and inject input signal to Pin 6. Monitor Pins 3 and 6 with two-channel scope. Lock should occur with 3 - 6 equal to 90o (phase error).
1994 Aug 31
7
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
6. If pulsed burst or ramp frequency is used for input signal, special loop filter design may be required in place of simple single capacitor filter on Pins 4 and 5. (See PLL application section) 7. The input signal to Pin 6 and the VCO feedback signal to Pin 3 must have a duty cycle of 50% for proper operation of the phase detector. Due to the nature of a balanced mixer if signals are not
BIAS ADJ 10k 2k
50% in duty cycle, DC offsets will occur in the loop which tend to create an artificial or biased VCO. 8. For multiplier circuits where phase jitter is a problem, loop filter capacitors may be increased to a value of 10 - 50F on Pins 4, 5. Also, careful supply decoupling may be necessary. This includes the counter chain VCC lines.
0.22F 10k HYSTERESIS ADJUST 2k
0.22F
+5V
1.2k FSK OUTPUT 16
1 FSK INPUT 0.1F 0.1F 1k 7 1k *NOTE: Use R9-11 only if rise time is critical. 510 +5V *510 11 300pF 4 5 300pF 3 9 2 6
10
15
14 NE564 12 33pF 13 8
10F/8V
0-20pF
SR01034
Figure 10. 10.8MHz FSK Decoder Using the 564
1994 Aug 31
8
Philips Semiconductors
Product specification
Phase-locked loop
NE/SE564
SR01035
Figure 11. Phase Comparator (Pins 4 and 5) and FSK (Pin 16) Outputs
BIAS ADJUST 10k
+5V .47F CER.
.47F CER.
I2
2k .33F
INPUT SIGNAL 6 fT 1k .47F DET. 7
2
1
10
4 5 11
LOOP FILTER .33F *510
510
NE564 9 VCO 3 8 12 13
VCO OUTPUT
NxfT CO *NOTE: Use R9-11 only if rise time is critical. f = NxfT /N
Figure 12. NE564 Phase-Locked Frequency Multiplier
1994 Aug 31
9

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